The Elusive Minimum: Total Phosphorus in Semiconductor Water

The question of a “minimum” total phosphorus requirement in chip-making water has no single numerical answer, because the limit depends on the standard tier and the process node rather than on one universal threshold. 

Phosphorus is usually controlled as phosphate, and the strictest published tier in China’s GB/T 11446.1—2013 sets a phosphate ceiling of 1 μg/L (approximately 1 ppb) for EW-I grade water. ASTM D5127 goes further for its most demanding classifications, with phosphate limits descending to 0.02 μg/L for Type E-1.2. SEMI F63, for its part, functions as a guide rather than a rigid rulebook, and its recommended anion figures for advanced nodes are expressed at the ppt level, reflecting what state-of-the-art treatment and metrology can achieve rather than a fixed “minimum”.

The reason phosphorus is held to such trace levels is twofold. It is an n-type dopant: even minute amounts contacting a wafer surface can introduce uncontrolled doping and disturb device uniformity. Phosphate also lowers resistivity, the most direct electrical measure of ultrapure water purity. 

In practice, a fab may set internal targets well below the published tier limit—sub-ppb for critical steps—while auxiliary processes operate at less stringent levels. What matters, then, is not a single minimum value but the tier appropriate to the process and the margin a facility maintains against contamination and analytical uncertainty.